Wm. A. Wulf and Sally A. McKee, “Hitting the memory wall: implications of the
obvious.” ACM SIGARCH Computer Architecture News 23(1), March 1995,
pp. 20–24. doi:10.1145/216585.216588
Five pages of arithmetic: if processor speed and DRAM latency improve at
different exponential rates, average memory access time comes to dominate
runtime regardless of cache hit rate. The wall follows from the growth rates
alone. It is not a design mistake anyone can correct, and thirty years later it
is still the organizing constraint of the field.
The interplay is the point
Three lanes, one axis. HBM appears in the interface lane bridging DRAM and
compute, exactly when compute is straining against GDDR. NVMe appears when SSDs
have outrun a protocol built for one slow mechanical actuator. CXL bridges all
three at once.
Select a milestone to see its summary and its sources.
NPU / computeDRAMStorageInterfaces16 milestones, 1968–2024
Select a milestone to see its summary and sources.
What this is
An index, not an encyclopedia. There are already many good introductions to
DRAM, and this is not another one. The valuable artifacts are the ones nobody
has assembled: sourced generation timelines with real spec deltas, an annotated
bibliography of the papers that mattered, a normalized accelerator comparison
that says out loud how each vendor constructs its TOPS/W claim, the readable
history of the industry, and honest maps of where public knowledge stops.
Most of the underlying material is genuinely public — JEDEC standards are free
after registration, NVM Express publishes openly, Micron publishes real
datasheets, and fifteen years of academic DRAM characterisation sits on arXiv.
It has just never been assembled in one place.
Verification over generation
Generated prose is nearly free and therefore nearly worthless, and this domain
is maximally hostile to unverified numbers. Every figure here carries a source
ID in structured data. Every source ID must resolve to a registry record with an
access date and a real archive snapshot. A pull request that adds an unsourced
number fails CI.
Where a fact has been extracted but not verified by a human, it sits in
quarantine/ and does not appear on this site.
Sources
Wm. A. Wulf, Sally A. McKee · ACM SIGARCH Computer Architecture News 23(1), pp. 20-24, 1995
The project's founding document and the origin of the phrase. Five pages of arithmetic showing that if processor speed and DRAM latency improve at different exponential rates, average memory access time comes to dominate total runtime regardless of hit rate — so the wall is a consequence of the growth rates alone, not of any fixable design choice. Cite it for the framing and the argument, not for device numbers, which are long obsolete. Publisher of record dates it March 1995; it is frequently cited as 1994 from its drafting and circulation.