Timeline
One shared time axis. NPU/compute, DRAM and storage run as parallel lanes, and interface events — HBM, NVMe, CXL — are drawn in their own lane with tie lines to the lanes they connect.
That arrangement is the argument for keeping these three domains in one repository. Read down a column instead of along a row and the causality shows up on its own: the memory-side responses arrive when the compute side runs out of bandwidth, not on some independent schedule of their own.
Select a milestone for its summary, its spec deltas, and its source cards. Each card carries the outbound link, the venue, the access date and the archive snapshot.
Loading timeline…
Select a milestone to see its summary and sources.
Reading the chart
- Year precision is marked as such. An event dated
2013is not claiming to know the month. Dates are recorded at the precision the sources support, and no further. - Interface events bridge lanes. The vertical tie lines connect an interface milestone to the domains it joins.
- Every milestone cites at least one source, and CI fails if an ID does not resolve to a registry record.
The lanes are currently uneven — DRAM is the deepest, storage and NPU the thinnest. That reflects what has been verified so far, not a judgement about what matters.