Citations here are data, not prose. Every source is a YAML record in
sources/registry/
with a stable ID, a DOI or URL, an access date, a licence, and a real Wayback
Machine snapshot captured at ingestion.
This page is generated from those records, ordered by how often the timeline cites them, which makes it a reading list as a side effect rather than a document anyone maintains by hand.
This project never mirrors content. It summarises enough to make you want the original and then hands you the DOI. Paywalled work is cited in full rather than avoided, with a pointer to the author preprint wherever one exists — for ISSCC, HPCA and ISCA papers, one usually does.
Note the access labels. A great deal of this material is free and widely assumed not to be: JEDEC standards, including DDR5 and the HBM line, are free to download after registering an account, and NVM Express publishes openly.
24 sources · 15 free to read (open or registration) · 6 with an author preprint ·24 with an archive snapshot
The one-transistor, one-capacitor DRAM cell as filed: 14 July 1967, granted 4 June 1968. Patents are the exception to this domain's secrecy — they are detailed by design, because disclosure is the price of the monopoly. Cite this for the cell's origin and priority date, and read it as the template for using the patent record where vendor documentation stops.
The project's founding document and the origin of the phrase. Five pages of arithmetic showing that if processor speed and DRAM latency improve at different exponential rates, average memory access time comes to dominate total runtime regardless of hit rate — so the wall is a consequence of the growth rates alone, not of any fixable design choice. Cite it for the framing and the argument, not for device numbers, which are long obsolete. Publisher of record dates it March 1995; it is frequently cited as 1994 from its drafting and circulation.
Announcement of Samsung's guilty plea, 13 October 2005, in the DRAM price-fixing prosecution; the third major manufacturer to plead after Hynix and Infineon. The entry point into the wider 2002-2006 record, which is the single richest public source on DRAM industry economics, because discovery and plea agreements put internal industry documents into the public domain that no vendor would otherwise publish.
Interview with the inventor of the one-transistor DRAM cell, conducted 20 July 2009 by Gardner Hendrie. First-person material for the history pillar: how the cell was arrived at, and how it was received inside IBM at a time when magnetic core was the incumbent. This is the class of source a model cannot fabricate convincingly, which is part of why the pillar exists.
The reference citation for gem5, whose memory-system models are the usual vehicle for published accelerator and memory-hierarchy studies. Relevant here as infrastructure rather than result: when a paper reports a bandwidth or latency figure from simulation, this is frequently the thing that produced it, and its configuration defaults propagate into a great many published numbers.
Project site and documentation for gem5, including its memory system models. Paired with the 2011 paper: the paper is the citation, the site is the thing you actually read when you need to know what a published simulated bandwidth number was measuring.
The publisher's own library of every ratified NVM Express specification, openly downloadable with no registration — genuinely public, unlike most storage interface documentation. The year records the 1.0 release; the page itself tracks the current spec family (Base, Command Set, Transport, MI). Use it to cite a specific revision, and record the revision in the citing page rather than pointing at the library alone.
Characterisation of 45 flash chips from six manufacturers, showing that as NAND scales down, density improves while endurance, latency and reliability all degrade — so the controller has to absorb an increasingly hostile medium. This is the storage-side counterpart to the DRAM characterisation vein: the numbers exist because the authors measured parts, not because vendors disclosed them. Open access, no paywall. Figures describe the parts tested and the nodes of the era; do not extrapolate them to current 3D NAND.
The original HBM standard and the anchor of the project's first content vertical. Free to download after registering a JEDEC account — the common belief that JEDEC standards sit behind a paywall is wrong and is worth correcting wherever it appears. The landing page returns 403 to automated clients, so the archive snapshot is the machine-readable copy of record. Edition dates for later revisions in the JESD235 line are not yet verified; see quarantine/.
Retention-time characterisation across a large population of real DRAM chips, and the standard citation for data-pattern dependence and variable retention time — two behaviours that make refresh a statistical problem rather than a fixed 64 ms rule. Useful precisely because refresh behaviour is documented in datasheets while the physics that forces the margin is not.
The paper that opened the RowHammer literature, and the best worked example of the project's reverse-engineering vein: characterisation of commodity DIMMs from multiple vendors, published because vendors would not disclose the behaviour themselves. Cite it for disturbance-error methodology and for the general finding that the effect is a scaling artefact rather than a defect. Per-vendor and per-module numbers are specific to the parts tested and should not be generalised to a process node or a generation.
Source for the simulator described in the 2016 CAL paper. Its per-standard timing tables and state machines are a compact, checkable encoding of how DDR, LPDDR, GDDR and HBM parts actually behave — often easier to read than the standard, and free, where the standard requires registration. Read the simulator to learn the part.
The paper describing the simulator whose source encodes per-generation DRAM timing and state machines. Pair it with the code record — reading a simulator's timing tables is a legitimate route to learning a part whose datasheet you cannot otherwise interpret, and this one covers many standards in one place.
The academic accelerator design that made data movement, rather than arithmetic, the explicit optimisation target — its dataflow exists to avoid DRAM accesses, on the argument that moving an operand costs far more energy than the multiply that consumes it. The clearest single citation for why accelerator design is memory-wall design. Extended from the ISSCC 2016 version (doi:10.1109/ISSCC.2016.7418007).
FPGA-based memory controller that issues arbitrary DRAM command sequences to real DIMMs, which is how most published timing-margin and retention results since 2017 were actually obtained. Read it to understand what commodity DRAM characterisation can and cannot establish, and to see which datasheet timing parameters turn out to carry large guardbands in practice.
The memory wall measured in a production accelerator rather than argued in the abstract. Its roofline analysis shows most of the evaluated neural network workloads sitting in the memory-bandwidth-limited region, and the abstract states that substituting the GPU's GDDR5 memory into the TPU would triple achieved TOPS — an accelerator whose headline compute number is gated by the memory it is attached to. 75 authors; the arXiv preprint is complete and freely readable. Also the reference point for how a vendor constructs a TOPS figure, since it documents its own conditions unusually honestly.
Publisher's page for the CXL specification family. CXL is the clearest current instance of the interfaces theme: a cache-coherent protocol layered on PCIe that lets memory be attached, pooled and shared outside the traditional DDR channel, which makes it storage and memory bending toward each other rather than a storage interface. The year records the 1.0 release; cite a specific revision for any figure.
Vendor explanation of what DDR5 changed and why, written for engineers rather than for press. Useful as a readable gloss on JESD79-5, and as a specimen of the one vendor that still publishes substantive technical documentation openly. Treat framing as vendor voice; treat the parameter descriptions as reliable but secondary to the JEDEC standard.
The DDR5 base standard. Authoritative for bank grouping, on-die ECC, the move of power management onto the module, and the timing parameter definitions that every DDR5 datasheet then instantiates. Free after registration. Later revisions (JESD79-5A, -5B, -5C) change numbers that matter; do not cite this record for a figure taken from a revision without recording which revision.
Current Ramulator implementation, restructured to make adding a standard or a controller policy tractable. Prefer it over the original when the target is a recent DRAM generation.
Current rewrite of Ramulator, and the more useful of the two for recent standards. Cite it rather than the 2016 paper when the question concerns a DRAM generation newer than DDR4.
Verified and ready to use. A source landing here is a prompt: it is material the project has checked but not yet built anything on.
Recorded lectures for the courses above, including full semesters on computer architecture and on memory systems. Cite a specific lecture rather than the channel when supporting a claim; the channel record exists so that the video vein is discoverable at all.
Entry point to full component datasheets: complete timing tables, mode register maps, refresh behaviour and speed bins, per part number. This is the most detailed openly published description of how a shipping DRAM part behaves, and the correct source for any concrete timing figure. It stops exactly where the trade secrets start — nothing here describes process integration, capacitor formation or yield.
Full graduate course with slides, readings and recorded lectures, all free. The memory-system lectures are the closest thing to a textbook treatment of modern DRAM internals, and the reading lists are themselves a curated bibliography worth mining for this registry. Companion recordings are on the Onur Mutlu Lectures channel.