In progress
This is the project’s first content milestone: every generation in the
JESD235 line, with complete spec deltas, fully sourced. It is deliberately the
only vertical being filled. Finished and narrow beats sprawling and sixty
percent complete.
The generation table below is intentionally empty. The figures exist and are
well known, and writing them from memory would take five minutes — which is
exactly the failure mode this project is built to prevent. They go in once they
are verified against the standards themselves, and the extraction candidates
are in quarantine/
until then.
Why HBM is the anchor
HBM is the clearest single instance of the project’s thesis. Faced with a
compute engine it could no longer feed, the industry did not make the memory
faster in the conventional sense. It made the interface wider and moved the
memory onto the package — trading the economics of a commodity DIMM for
proximity and bus width.
The TPU paper is the other half of the same story from the compute side:
production accelerator workloads sitting in the bandwidth-limited region of a
roofline, with the paper’s own counterfactual showing achieved throughput
gated by the attached memory rather than by the arithmetic.
Generation table
| Generation |
Standard |
Published |
Status |
| HBM |
JESD235 |
2013 |
Spec deltas pending verification |
| HBM2 |
JESD235A |
— |
Edition date unverified — quarantined |
| HBM2E |
JESD235C / JESD235D |
— |
Unverified — quarantined |
| HBM3 |
JESD238 |
— |
Unverified — quarantined |
| HBM3E |
JESD238A |
— |
Unverified — quarantined |
| HBM4 |
— |
— |
Not yet ingested |
Each row will carry, once sourced: bus width, channel and pseudo-channel
organisation, per-pin data rate, per-stack bandwidth, stack height, capacity per
stack, and the supply voltage — with the standard revision that establishes each
figure attached to that figure, not to the row.
What is public here
The JESD235 line is free to download after registering a JEDEC account. The
common assumption that it sits behind a paywall is one of the reasons this
material is less widely understood than it should be.
Sources
standardFree, registration requiredJEDEC Solid State Technology Association · JESD235, 2013
The original HBM standard and the anchor of the project's first content vertical. Free to download after registering a JEDEC account — the common belief that JEDEC standards sit behind a paywall is wrong and is worth correcting wherever it appears. The landing page returns 403 to automated clients, so the archive snapshot is the machine-readable copy of record. Edition dates for later revisions in the JESD235 line are not yet verified; see quarantine/.
paperPaywalled — preprint availableNorman P. Jouppi, Cliff Young, Nishant Patil, David Patterson · ISCA 2017 (44th Annual International Symposium on Computer Architecture), pp. 1-12, 2017
The memory wall measured in a production accelerator rather than argued in the abstract. Its roofline analysis shows most of the evaluated neural network workloads sitting in the memory-bandwidth-limited region, and the abstract states that substituting the GPU's GDDR5 memory into the TPU would triple achieved TOPS — an accelerator whose headline compute number is gated by the memory it is attached to. 75 authors; the arXiv preprint is complete and freely readable. Also the reference point for how a vendor constructs a TOPS figure, since it documents its own conditions unusually honestly.