NPU / compute
This is the lane where entry is genuinely tractable for small teams. RISC-V, open PDKs and cheap shuttle runs mean an accelerator design is a real project for a handful of people, in a way that a DRAM fab never will be. Depth here is directly actionable, and the project weights effort accordingly.
It is also the lane where the memory wall shows up most plainly. Accelerator design is, in practice, memory design: the arithmetic is cheap and the operand movement is not.