Telling a reader where the wall of secrecy actually sits is a service. Most writing on DRAM either implies everything is knowable or implies nothing is. Neither is true, and the boundary is sharp enough to draw.
The standard itself. JEDEC’s DDR5 specification defines bank grouping, on-die ECC, the module-level power management architecture, and the timing parameter definitions every datasheet then instantiates. Free after registering an account — the widespread belief that it is paywalled is simply wrong.
How a shipping part behaves. Micron publishes complete component datasheets: timing tables, mode register maps, refresh behaviour, speed bins, per part number. This is the most detailed open description of a real DRAM device that exists, and it is the correct source for any concrete timing figure.
What the datasheet does not admit. Academic characterisation has measured the margin the datasheets keep. Retention behaviour turns out to be data-pattern dependent and to vary over time in the same cell, which makes refresh a statistical problem rather than a fixed interval. Repeatedly activating a row disturbs its physical neighbours. Neither behaviour appears in vendor documentation; both are established on commodity parts by researchers with an FPGA and a DIMM.
That last vein exists because of the secrecy. It is the best material available on real device behaviour, and it is fully open.
| Area | Status |
|---|---|
| Cell array architecture, banking, interface | Public — standards and datasheets |
| Timing parameters, mode registers, refresh | Public — vendor datasheets |
| Real-world retention, disturbance, margin | Public — academic characterisation |
| Process integration and flow | Dark |
| Capacitor formation, high-aspect-ratio etch | Dark |
| Dielectric stacks and materials | Dark |
| Yield learning, defect density, binning economics | Dark |
The line is not arbitrary. Everything above it is something a customer must know to use the part, or something a researcher can measure from outside. Everything below it is what actually distinguishes three companies that all sell a standardised commodity, which is precisely why none of them discuss it.
Patents and litigation records are the partial exception, and the history pillar uses both. A patent discloses by design; discovery discloses by compulsion. Neither gets you a process flow.
If you are trying to learn how DRAM works, the public record is genuinely sufficient and mostly free. If you are trying to learn how DRAM is made well enough to make it, the public record stops well short, and no amount of persistence closes that gap.
Pages in this project will say which side of that line a claim comes from rather than blurring the two.
The DDR5 base standard. Authoritative for bank grouping, on-die ECC, the move of power management onto the module, and the timing parameter definitions that every DDR5 datasheet then instantiates. Free after registration. Later revisions (JESD79-5A, -5B, -5C) change numbers that matter; do not cite this record for a figure taken from a revision without recording which revision.
Entry point to full component datasheets: complete timing tables, mode register maps, refresh behaviour and speed bins, per part number. This is the most detailed openly published description of how a shipping DRAM part behaves, and the correct source for any concrete timing figure. It stops exactly where the trade secrets start — nothing here describes process integration, capacitor formation or yield.
Vendor explanation of what DDR5 changed and why, written for engineers rather than for press. Useful as a readable gloss on JESD79-5, and as a specimen of the one vendor that still publishes substantive technical documentation openly. Treat framing as vendor voice; treat the parameter descriptions as reliable but secondary to the JEDEC standard.
Retention-time characterisation across a large population of real DRAM chips, and the standard citation for data-pattern dependence and variable retention time — two behaviours that make refresh a statistical problem rather than a fixed 64 ms rule. Useful precisely because refresh behaviour is documented in datasheets while the physics that forces the margin is not.
The paper that opened the RowHammer literature, and the best worked example of the project's reverse-engineering vein: characterisation of commodity DIMMs from multiple vendors, published because vendors would not disclose the behaviour themselves. Cite it for disturbance-error methodology and for the general finding that the effect is a scaling artefact rather than a defect. Per-vendor and per-module numbers are specific to the parts tested and should not be generalised to a process node or a generation.
FPGA-based memory controller that issues arbitrary DRAM command sequences to real DIMMs, which is how most published timing-margin and retention results since 2017 were actually obtained. Read it to understand what commodity DRAM characterisation can and cannot establish, and to see which datasheet timing parameters turn out to carry large guardbands in practice.
Full graduate course with slides, readings and recorded lectures, all free. The memory-system lectures are the closest thing to a textbook treatment of modern DRAM internals, and the reading lists are themselves a curated bibliography worth mining for this registry. Companion recordings are on the Onur Mutlu Lectures channel.